The OpenCore ® feature in the Quartus II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and postcompilation simulation support.
The following topics show how to create and instantiate some of these functions:
You can use the MegaWizard Plug-In Manager to create content-addressable memory (CAM), ClockLock ® PLL, LVDS, and RAM functions. To use megafunctions in the design, use the MegaWizard ® Plug-In Manager (Tools menu) to generate and instantiate a megafunction variation.
vo) from imported VQM Files for simulation in other EDA simulation tools, the Quartus II software does not retain the order of ports. When connecting ports in the Verilog Design File, make sure you connect ports by name instead of by order. bdf) or other proprietary Altera ® formats. Only describe the design with Verilog or VHDL the Synplify software cannot synthesize Block Design Files (. Set Up the Synplify Working EnvironmentĮnter a VHDL or Verilog HDL design in the Quartus II Text Editor or another standard text editor and save it in your working directory. If you have not already done so, perform 1. To create a Verilog or VHDL design for use with the Synplify software: You can create Verilog HDL design files with the Quartus ® II Text Editor or another standard text editor for use with the Synplicity Synplify software. Set Up a Project with the Synplify Software
Using the Synplify Software with the Quartus II Software Using the Quartus II Software with Other EDA Tools